4 Bit Ripple Carry Adder(A small Project)

November 3rd, 2006, 11:17 pm

Objectives:-
•  To be familiar with the ModelSim Logic Simulator .


  Step 01:   Load ModelSim.


  Step 02:  Create or Load Project.


  Step 03:  Edit and Compile Verilog File.


  Step 04:  Simulate Verilog Module.


  Step 05:  Study the results either in list (tabular form) or Waveform and verify.


•  To describe 4-bit ripple carry adder digital circuit at gate level in Verilog HDL.


•  To simulate the functionality of Verilog module under test. (Verilog test bench).


•  To analyze the results directly from the waveform and verify the functionality.


Filed under Uncategorized, Verilog HDL · Comments

4 Bit Ripple Carry Adder(A small Project)

November 3rd, 2006, 11:17 pm

Objectives:-
•  To be familiar with the ModelSim Logic Simulator .


  Step 01:   Load ModelSim.


  Step 02:  Create or Load Project.


  Step 03:  Edit and Compile Verilog File.


  Step 04:  Simulate Verilog Module.


  Step 05:  Study the results either in list (tabular form) or Waveform and verify.


•  To describe 4-bit ripple carry adder digital circuit at gate level in Verilog HDL.


•  To simulate the functionality of Verilog module under test. (Verilog test bench).


•  To analyze the results directly from the waveform and verify the functionality.


Filed under Uncategorized, Verilog HDL · 2 Comments

I have started DLD Lab 06.

November 2nd, 2006, 6:49 pm

Welcome to Rizwan Abbasi’s Blog.

I am in university now doing the lab assignment of DLD in MODELSIM.

Soon i will make this blog functional.

 

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Completed DLD LAB 06

November 2nd, 2006, 6:47 pm

It’s 11:45 PM and i have completed my DLD Lab work allmost(in Model Sim). Some documentation is left which i will complete in home on weekend.

                       It was very difficult lab and took alot of time. I have to view the code several times to catch the errors.

 In my next post i will write the code of my LAB 06 because it’s near to 12:00 PM and lab is closing.

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